1. Technical Field
The present invention relates to a semiconductor wafer and a method of inspecting a semiconductor wafer.
2. Related Art
Attempts have been made to develop techniques of growing Group-III nitride semiconductor crystals on Si wafers. For example, Japanese Patent Application Publication No. 2013-021124 discloses a Group-III nitride epitaxial wafer, which is provided for the purposes of reducing the cracks that may occur during the step of forming devices. The Group-III nitride epitaxial wafer includes a Si wafer, an initial layer that is in contact with the Si wafer, and a superlattice stack structure formed on the initial layer and including a plurality of stacks each of which sequentially includes a first layer made of AlGaN having an Al ratio of more than 0.5 and no more than 1 and a second layer made of AlGaN having an Al ratio of more than 0 and no more than 0.5 and is characterized in that the Al ratio of the second layer gradually decreases in a direction away from the substrate.
For example, Japanese Patent Application Publication No. 2010-232322 discloses a compound semiconductor wafer that has reduced cracks, crystal defects and warping in a nitride semiconductor layer and can achieve improved productivity. The compound semiconductor wafer includes a silicon monocrystalline wafer having a crystal plane orientation denoted as the (111) plane, a first buffer layer formed on the silicon monocrystalline wafer and made of monocrystalline AlxGa1-xN (0<x≤1), a second buffer layer formed on the first buffer layer and including a plurality of first unit layers and a plurality of second unit layers that are alternately stacked, each first unit layer being made of monocrystalline AlyGa1-yN (0≤y<0.1) and having a thickness of no less than 250 nm and no more than 350 nm, each second unit layer being made of monocrystalline AlzGa1-zN (0.9<z≤1) and having a thickness of no less than 5.0 nm and no more than 20 nm, and a semiconductor element forming region formed on the second buffer layer and including one or more nitride-based semiconductor monocrystalline layers.
For example, Japanese Patent Application Publication No. 2008-171843 discloses a semiconductor electronic device that can achieve both reduced warping in the wafer and further reduced leakage currents. The semiconductor electronic device is a semiconductor electronic device including a compound semiconductor layer stacked on the wafer with a buffer layer placed therebetween. The buffer layer includes a compound layer in which a second layer is stacked on a first layer. The first layer is made of a nitride-based compound semiconductor having an Al ratio of 0.2 or lower and the second layer is made of a nitride-based compound semiconductor having an Al ratio of 0.8 or higher.
Y. Ohba. R. Sato, J. Crystal Growth 221, 258 (2000), G. Sarusi et al., J. Electron. Mater. 35, L15 (2006) and M. Tungare et al., J. Appl. Phys. 113, 163108 (2013) disclose techniques of forming an AlN layer on a Si wafer. Y. Ohba. R. Sato, J. Crystal Growth 221, 258 (2000), G. Sarusi et al., J. Electron. Mater. 35, L15 (2006) and M. Tungare et al., J. Appl. Phys. 113, 163108 (2013) disclose microscopic images of the front surface of the AlN layer formed on the Si wafer. The images show that many holes are formed in the AlN layer.
K. Matsumoto et al., J. Vac. Soc. Jpn. 54, 6 (2011), p 376-380 discloses as follows: “if it is possible to grow and alternately stack GaN and AlN on each other in such a manner that the AlN on the GaN is relaxed and the GaN on the AlN has compressive stress, it is expected that the GaN/AlN strained layer super-lattice (hereinafter, referred to as SLS) structure can be used to allow the entire film to have compressive stress. It also seems possible to add compressive stress by employing other combinations than the SLS structures, as long as any upper film has a larger lattice constant than its lower film in the combinations.”
When a Group-III nitride semiconductor layer is formed on a Si wafer, the wafer may be warped and the Group-III nitride semiconductor layer may crack due to the difference in thermal expansion coefficient between Si and the Group-III nitride semiconductor crystal. To address this issue, as disclosed in the above-mentioned patent and non-patent documents, a layer in which internal compressive stress is generated (hereinafter, may be referred to as the stress generating layer) is formed in order to balance the generated compressive stress and the tensile stress generated in the nitride crystal layer due to the difference in thermal expansion coefficient. In this way, the semiconductor wafer is prevented from being warped when room temperature is restored, and the Group-III nitride semiconductor layer is prevented from cracking.
When used to reduce the warping of the semiconductor wafer, however, the stress generating layer is designed to reduce the warping of the semiconductor wafer that may be observed once the temperature of the wafer has changed back to room temperature. Therefore, the wafer is warped while the epitaxial growth is taking place, during which the temperature of the wafer is kept high. If the wafer is warped, it is difficult to equalize the micro-level growth conditions across the entire front surface of the wafer. Here, the micro-level growth conditions greatly affect the characteristics such as the crystal quality and the sheet resistance. Therefore, it is difficult to maintain uniform characteristics such as the crystal quality across the entire region in the wafer plane while, at the same time, reducing the warping of the wafer that may be observed at room temperature. In particular, when a large Si wafer having a diameter of 6 inches or the like is used, it becomes even more difficult to reduce the warpage of the wafer that may be observed once the temperature of the wafer has changed back to room temperature and, at the same time, to maintain uniform characteristics such as the crystal quality since the warpage of the wafer during the epitaxial growth is also larger.
When the Group-III nitride semiconductor layer is formed on the Si wafer, a reaction suppressing layer is positioned between the Si wafer and the stress generating layer in order to suppress the reaction between the Si atoms constituting the Si wafer and the Ga atoms included in the Group-III atoms. The inventors of the present invention, however, have acknowledged through experiments and their studies that the reaction suppressing layer is capable of suppressing the reaction between the Si atoms and the Ga atoms and also greatly affects how much the wafer is warped depending on the state of the interface between the Si wafer and the reaction suppressing layer. Accordingly, it is necessary to appropriately control the growth of the reaction suppressing layer in order to efficiently protect the front surface of the Si wafer and appropriately reduce the warping of the wafer.
The objective of the present invention is to provide a semiconductor wafer that is obtained by forming a Group-III nitride semiconductor layer using epitaxial growth on a Si wafer, where the Group-III nitride semiconductor layer can achieve satisfying characteristics such as the required withstand voltage, the physical properties such as the sheet resistance reliably achieve in-plane uniformity, and the semiconductor wafer is warped only a little. In particular, the objective of the present invention is to provide a semiconductor wafer that reliably achieve the required characteristics and the in-plane physical property uniformity and that is warped only a little as described above even when a large Si wafer having a diameter of 6 inches or more is used. Another objective of the present invention is to provide a semiconductor wafer that is capable of reliably achieving the required characteristics and the in-plane uniformity and reducing the warping as described above while the front surface of the Si wafer is efficiently protected.